1. Field of the Invention
The invention relates to the planarization of glass layers used in semiconductors.
2. Prior Art
Glass layers are frequently used in the fabrication of semiconductor integrated circuits. For example, these insulative layers are used in metal-oxide-semiconductor (MS) circuits over polysilicon members to insulate them from overlying metal lines, and between layers of metal lines.
When a glass layer is deposited over underlying members an undulating contour frequently results. When a metal layer is formed on this surface, several problems occur which are a direct result of the non-planarized surface. For instance, stress cracks can occur in the metal at abrupt corners and voids beneath the metal.
An early solution to this problem consisted of reflowing the glass layer after its formation. See U.S. Pat. No. 3,825,442. It is not always possible to reflow the glass layer. This reflow does not provide a sufficiently planar surface for overlying metal layers in many processes.
Another solution to this problem is to planarize (e.g., flatten) this glass surface through etching. In one technique a spin-on-glass is formed on the surface. The spin-on-glass, because of the spinning during formation, provides a planar surface. Then a plasma etching step is used which etches away both the spin-on-glass and deposited glass until a planar surface of the deposited glass is reached. This technique is described in "A Planarization Process for Double Metal CMOS Using Spin-on-Glass as a Sacrificial Layer" by Elkins, Reinhart and Tang, IEEE V-MIC Conference, June 9-10, 1986. For other uses of spin-on-glass, see U.S. Pat. No. 4,587,138. Also see application Ser. No. 870,234, Filed June 3, 1986, entitled ETCH-BACK PLANARIZATION FOR DOUBLE MEAL VLSI, and assigned to the assignee of the present invention.
The present invention is an improvement on the process described in the above-referenced article.